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Alcatel-Lucent Interior Routing Protocols and High Availability












Alcatel-Lucent Interior Routing Protocols and High Availability practice test
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Plan forward For A successful SoC-based PCB Design

in the building of SoC-based (system-on-chip) circuit boards, the SoC’s further capabilities will supply abundant purposeful merits. but at the identical time, these capabilities can introduce extra challenges to the circuit board manufacturing process. therefore, setting up a superb plan for designing, establishing, trying out, and producing the final printed-circuit boards (PCBs) is first rate enterprise observe.

a number of steps in the PCB construction technique encompass areas that permit enhancements that may increase the convenience of board manufacturing and the yield rate of the construction circuit boards. Many points of the procedure, from the SoC itself to the design system to the conclusion board checks, should be reviewed for improvements that may have an effect on the PCB’s remaining manufacturability.

measurement Does count

SoC contraptions have a undeniable inherent complex nature. an entire device is packed right into a single silicon kit the dimension of your thumbnail. there are lots of interfaces, clocks, alerts, protocols, and power connections within a small physical structure. The reduction in the dimension of the gadget doesn't guarantee a discount in PCB implementation issues. In some circumstances, this physical discount raises the number of challenges that should be encountered when designing the underlying PCB.

To healthy so many combinations of feature within the same small package, the chip’s designers usually use a suave method of assigning distinct combinations of function to the same pin. On the Texas devices (TI) Sitara AM3358 processor, for instance, the identical pin may also be assigned UART, I2C, customary-intention I/O (GPIO), reduced Gigabit Media independent Interface (RGMII) Ethernet, or motor drive pulse-width modulation (PWM) features, representing simplest a couple of of the attainable interfaces.1

This use of temporal task of diverse interfaces on the same actual structure, the I/O telephone, is a superb means of constructing a cost-effective equipment solution. in many methods this can support reduce the basic gadget can charge and take expertise of ever-shrinking silicon procedures. the use of I/O pin multiplexing like this may latest some challenges at the PCB stage, although.

implementing a gadget using an SoC with a fancy I/O pin multiplexing scheme presents a challenge in that the identical PCB design isn't premier for the entire feasible I/O pin definition mixtures. determine 1 shows the PCB design for 2 different I/O selections from the same SoC. In circuit design A, a set of pins is configured for a UART, an SD/MMC card, GPIO, and motor manage. In circuit design B, the same set of pins is configured for an Ethernet bus using the RGMII classification of interface.

be aware that at a schematic stage, there does not appear to be tons problem altering between the two designs seeing that it’s readily changing the conclusion contraptions/circuits with the appropriate choices (equivalent to an RS-232 transceiver versus the Ethernet actual layer, or PHY). despite the fact, when the PCB layout implementation is reviewed, a dramatic change in the requirements for the diverse interfaces exhibits what main changes have to be made to the PCB placement and subsequent routing to increase a strong circuit board. The UART, SD/MMC card, GPIO, and motor handle could be routed to multiple gadgets that could be positioned at spatially distinct positions on the PCB. In contrast, the Ethernet bus should be routed to a single equipment, the Ethernet PHY, as a way to probably be placed pretty near the SoC.

This change within the routing of the identical SoC pins depending on the interface connection exhibits why there is not a single world appropriate way to put out an SoC-primarily based PCB that works for all designs. as an alternative, each design needs consideration to such particulars to lower the risk of manufacturability concerns. Reference designs from the SoC manufacturer can assist exhibit pragmatic implementations of commonplace circuit designs.

1. The ability of the SoC to connect different sets of functional signals from the same sets of pins can create quite a difference in a board layout. These layouts show examples of the diverse differences in routing between two different implementations of the same SoC. In the first example, the pins are used for a UART, SD/MMC card, GPIO, and motor control. In the second example, the same pins are used for an RGMII Ethernet PHY connection.1. The potential of the SoC to join diverse sets of functional signals from the equal sets of pins can create reasonably a difference in a board layout. These layouts demonstrate examples of the distinctive alterations in routing between two distinct implementations of the equal SoC. within the first illustration, the pins are used for a UART, SD/MMC card, GPIO, and motor manage. within the second illustration, the identical pins are used for an RGMII Ethernet PHY connection.

Planning ahead

by the time the primary PCBs arrive, many design issues will also be checked. The system of designing the PCB in an effective manner has lots to do with what gadgets can also be established early within the design. The steps within the procedure can aid stream the high-chance gadgets previous within the system to give you more time to recover from possible error in the design or implementation. however, one of the PCB design system have to be cautiously notion out to meet the pre-requisites of every step (Fig. 2).

2. This diagram shows a simplified graphical example of the type of flow in a standard PCB development process. The main steps within the process are encapsulated as the major blocks within the design flow. 2. This diagram suggests a simplified graphical example of the classification of flow in a standard PCB construction procedure. The main steps inside the technique are encapsulated because the important blocks within the design flow.

In a standard PCB build environment, the leading goal, of route, is to make use of the schematic design to build a tangible precise PCB. several distinct materials will also be used to generate the circuit board. For this discussion, inflexible FR-four cloth is believed to be used. The complex physical and material qualities of the FR-four copper-clad glass epoxy board are past the scope of this article. besides the fact that children, these very particulars of the PCB fabric can make contributions to vital design choices, beginning with the requirements of the board the entire method through trying out and construction manufacturing. As part of the PCB requirements and design steps, it helps to remember these particulars because details similar to copper weight and board inventory insulation thickness will examine the stackup and steer the routing constraints for the board.

In some cases, it will probably appear easy to depart the board actual parameters to the layout person. but preserving even a cursory expertise of the underlying board substrate can permit stronger selections that have an effect on many objects going returned to certain features akin to how large the board can be and what gadgets may also be positioned on the PCB.

as an example, FR4 material has a certain quantity of flexibility throughout its lateral and longitudinal dimensions. If here is no longer addressed, then a ball grid array (BGA) the size of an SoC may influence in solder ball bond failure if unexpected mechanical stress is positioned on the board. In a unique way, mounting the PCB can add to considerations of thermal failure and board twist/mechanical flexing reckoning on the enclosure/rack meeting.

notwithstanding firstly view of the PCB design technique, the end production board is the key metric to be seen, the use of and precise need for early prototype circuit boards is a vital step in the standard PCB move. regardless of a careful view of the design exercise and checklists that investigate that design constraints were met, errors within the design can slip via and show up in the final board. hence, early prototype boards are essential for flushing out blunders and misjudgments in a SoC board design.

What errors can happen when there has been due diligence during the design of a circuit board? a couple of issues can go wrong with even the superior-intentioned SoC-based mostly circuit board design:

  • verbal exchange mistakes between the board designer, necessities team, layout person, or board manufacturing accomplice
  • Too tremendous a scope of the design leaving unhandled requirements
  • part footprint blunders
  • Mechanical placement blunders (connector/cable clearance issues, monitor mounting complications, and so forth.)
  • Misunderstanding of the board necessities
  • Electrical design blunders
  • energy provide issues
  • Interface sign noise complications
  • Orientation of gadget/daughterboard connectors
  • Error within the handle project of gadgets
  • Board configuration alternative practical considerations
  • component availability problems
  • element revision alterations through the manufacturer
  • establishing goals

    Simulation know-how has greater pretty in contemporary years, and tools using it will also be used to try to trap some of those sorts of issues. whereas a huge effort to simulate the design, check mechanical clearance, confirm design requirements, and feel via how configuration alternate options can reduce talents errors (and all these activities are decent design practices), the enhance of the design agenda to achieve all of these steps realistically can be greater than the board construction constraints will permit.

    It is terribly crucial to force to clear and succinct design dreams as an early a part of the PCB design technique. These design goals can seem everyday and nebulous before expounding on them all through the design part. goals which are left indistinct go away an opportunity for misunderstanding, so that you can manifest as PCB faults that can have an effect on the easy build time table of the closing PCBs.

    as an instance, if a specific NAND flash memory need to be used, however the I/O voltage level is not clear, then the circuit could be designed for helping each 1.eight V and 3.three V or it may well be designed for a single voltage value. For seamless connection to the SoC, this I/O voltage degree need to be matched on the corresponding provide rail on the SoC. this may add unneeded complexity and possibility to the board. When there is any doubt about necessities, studies can make clear these questions.

    component placement upon the circuit board has large effects on the manufacturability of the last PCB. The optimum placement of the components influences inter-equipment clearance, manufacturing decide upon and region efficiency, cable access and clearance, and soldering profile transformations. this is distinctive than the I/O multiplexing issues explained prior, youngsters they are often related.

    considerations equivalent to lead versus lead-free add-ons placed next to each and every other can make it extra tricky to set the suitable soldering profile for the board. (here's much less of an issue now with advancements in soldering expertise.) typically, lead-free add-ons require a far better solder similar to 250°C while lead add-ons can also require 220°C.2 putting these add-ons appropriate next to every other may affect manufacturability as a result of differential thermal convection. here's especially true for ultra-small BGA accessories (equivalent to single gates in discrete packages) that have best a number of balls for attachment and decrease thermal mass.

    If one certain component has inflexible routing constraints, this may also restrict the placement of different components within a certain vicinity. as an instance, excessive-pace interfaces comparable to DDR3 require constant reference planes and beneficial isolation from different interfaces. this will limit placement of alternative contraptions within a undeniable distance of the DDR3 reminiscence gadgets.

    In a SoC classification of design, many heterogeneous peripheral instruments often ought to function on the same PCB. making ready a precedence-based mostly placement analysis can support make sure a correct functioning final circuit board. flooring-planning the PCB prior to component placement helps to demonstrate abilities routing, vigor, and mechanical issues.

    usually a circuit board has definite physical constraints for connector placement in keeping with the deliberate makes use of of the PCB and the conclusion product that it's in. every now and then the SoC has distinct sets of I/O to which a selected interface will also be mapped. using a ground plan of the PCB can show better combinations of I/O mapping of the SoC pins that will give stronger mechanical constructions on the circuit board.

    On The Board

    the location in determine 3 will evidently supply a much better board it's more convenient to lay out and construct than the different board. The flooring plan has the devices spatially top of the line for routing considering that the locations of the acceptable SoC balls for each interface are oriented close the position of the external equipment on the board. determine 4 illustrates a ground plan that has the components positioned away from the corresponding interface balls on the SoC processor. this can require routing lanes that move each and every other and eat effective board energy and sign routing enviornment. bear in mind, there are best so many layers to route alerts and power and price increases to benefit greater layers for routing.

    3. This example shows a placement that supports optimal routing with regards to signal trace locations. three. This illustration shows a placement that helps choicest routing related to signal trace areas. 4. This example shows a placement/floorplan that will make routing more difficult and costly since it requires more physical locations for the signal traces. 4. This example shows a placement/floorplan with a view to make routing greater complicated and expensive because it requires greater actual locations for the signal traces.

    while this might also look evident when searching at the design at this degree, on occasion different board requirements similar to connector placement will force non-most excellent placements to occur. searching on the flooring plan of the board can demonstrate considerations that may not be intuitive when when you consider that best the electrical connections of the schematic.

    As a typical rule in an SoC-based design, escaping the SoC’s ball array is of basic challenge, no longer just for alerts however also for energy and floor connections. If a reasonably-priced PCB is a crucial constraint, then there are limitations to how the indicators may also be routed from the entire balls on the SoC kit. for instance, in a 15- via 15- by means of 0.8-mm package with most of the ball array populated, routing get away will also be greater elaborate if the supporting add-ons are positioned in poor areas or at distances from the SoC that don't seem to be conducive to the deliberate board measurement.

    Splitting the design into varied boards for anything motive can enhance the complexity. If the board constraints require numerous boards, further planning and verification are integral to retain signal integrity on vital interfaces in addition to to make sure mechanical clearances are relevant.

    here is another instance of the usage of early prototypes to bolster the spatial part analysis and assess that there usually are not creation issues. The introduction of the second (or extra) boards to the physical construction adds another dimension where add-ons may also intervene with each and every different the place they wouldn’t on a single PCB solution.

    making ready For Contingencies

    As foolproof as modern add-ons have gotten, it remains important to investigate the deliberate add-ons for a PCB design to aid minimize have an effect on to the end board build. Some add-ons have under apparent packaging details. whereas standard packages exist for a lot of ICs and discrete add-ons, some programs have abnormal attributes that make them prone to soldering error and different assembly errors akin to non-usual pin pad geometries or assignments.

    for example, in figure 5, the short-term pushbutton swap would appear initially look to have pins 1 and 2 shorted collectively and 3 and 4 shorted collectively according to the proximity of every pair of pins. however the machine schematic from the datasheet indicates that the other sets of pins are definitely linked.

    5. This diagram shows how the pin locations of a component can be counterintuitive to the pin definitions. 5. This diagram indicates how the pin places of a element will also be counterintuitive to the pin definitions.

    the use of accessories with these styles of irregularities introduces greater possibility into the average PCB design flow. while the irregularity may also be compensated for, it is convenient to leave out these particulars when there are such a lot of different particulars to investigate and check just before sample technology for PCB fabrication.

    a tremendous subject for manufacturability of a board rests with the component alternative. As hardware board designers, they always pay attention to the board details. but the essential details concerning the add-ons such because the product lifetime of the chosen components for the design can spell disaster for a board build schedule if the supply of the chosen gadgets is a problem.

    A worse case is that if the component isn't any longer purchasable without a alternative device or 2nd sources purchasable. The PCB then continually need to be redesigned to accommodate a substitute component. delivered to this redesign is the obtrusive challenge about checking whether the brand new element will cause any new complications that had already been answered for the old part. An SoC-based design may also have additional necessities if there's a detailed coupling of the SoC to some external devices.

    As mentioned prior, the PCB material can also have most important implications for the manufacturability of a SoC-based design. The construction of the PCB itself might be dictated via one of the crucial normal design necessities corresponding to can charge, size, board define, and extra. normal board constraints demand “smaller is enhanced” when it pertains to universal PCB physical measurement. Smaller physical dimension decreases the volume of space for routing traces and placing components. When since solutions to placement and routing issues caused by using any cause, simple alterations comparable to simply adding extra layers to the PCB could at first seem to be appealing but may now not be the correct answer.

    trust a one hundred twenty- by using 95-mm PCB with a central SoC processor it truly is in a 17- by means of 17-mm equipment with a 625-ball array in a 0.65-mm pitch. There might be other contraptions on the board, and some of them could be BGA-classification applications. The most important problem in appropriate design of the PCB could be the routing break out from the SoC. depending on the variety of indicators really used on the SoC for the design, routing each and every SoC pin to the target on the PCB can be challenging.

    whereas the indicators are one element to the routing job, the vigour distribution community (PDN) is simply as essential. In these days’s modern SoC processors, the vigour beginning is terribly essential to cut erratic runtime failures, which can be elaborate to diagnose. here's where one solution doesn't work for all implementations. If charge and time table were no difficulty, then a typical solution could be just to increase the layer count and use greater complex and smaller by way of types (Fig. 6).

    6. The capability to use interior layers to route signals is an important benefit of using smaller blind and buried vias. However, this benefit should be weighed against the additional cost of the board.6. The means to use indoors layers to route indicators is an important benefit of the use of smaller blind and buried vias. youngsters, this benefit should still be weighed towards the further cost of the board.

    This method effectively compensates for the reduction in gross spatially X&Y routable enviornment and volume (bear in mind, routing is in 3D) when the usual board dimension is reduced in size by means of decreasing the physical quantity of the signal and power vertical transition zones (vias) and lengthening the routable Z-axis enviornment. The draw back to here's that each and every extra layer pair delivered raises the PCB cost and time.

    furthermore, the use of the rest apart from via-hole vias of a selected diameter and pad size will boost the fabrication steps due to the requirement to drill earlier than fabrication adhesion of outer layers. also, the usage of non-mechanical drills as a result of the small diameter by way of physical dimension will enhance the PCB fabrication cost. The industry has more desirable lots during this area over the remaining decade, however 12-layer boards with micro-vias and blind/buried vias are nevertheless no longer equal in can charge with 4- or six-layer boards with via-gap vias simplest.

    checking out And The huge photograph

    every design should still be evaluated separately to assess the most suitable answer. as an example, the SoC will customarily have a enormous volume of routing running to it, and it'll also demand a good amount of vigor network planes, partial planes, or wide traces. including layers will frequently aid in routing escape from the SoC, but the further charge of the PCB with the added layers might also not be tolerated from an conclusion-can charge point of view.

    It’s essential to specify and track the particular placement and sign design constraints for the board. The very procedure of specifying these constraints may flush out some competing requirements that can also be resolved early on. at the very least, these constraints help to book layout from a greater proactive stance in a gaggle-classification organization. This really helps to show the essential alerts similar to DDR3, MIPI, Ethernet RGMII, and greater, as well as how these alerts deserve to be prioritized throughout placement and layout to improve their traces’ sign integrity.

    in spite of everything, because of definite sign integrity requirements of some interfaces, a PCB physical enviornment may have certain prime routing areas that command brief distance between selected add-ons, brilliant reference plane locations, and sooner wavefront flight times due to layer qualities. by focused on the essential nets to occupy these major routing locations, the resulting PCB has a reduce risk of board failure due to crosstalk concerns, vigor supply noise issues, component tolerance issues, and beyond.

    besides the fact that a design is confirmed to function inside specification, there is not any be sure that every creation unit will feature inside that specification. because of the various variables linked to building a latest SoC-primarily based circuit board, gadgets equivalent to part tolerance, soldering mishaps, meeting mistakes, PCB fabrication errors, design issues, and simple human error may cause yield problems in production PCBs.

    for this reason, a correct board construction process that seeks high yield of ultimate circuit boards should still include some category of diagnostic checking out. These exams should still be run on each production board earlier than it's packed and shipped. SoC processor-type boards encompass distinctive heterogeneous interfaces that every one have particular practical necessities. hence, the diagnostic assessments should encompass a test or sequence of exams for every of these interfaces. figuring out and obviously defining the requirements of the board will pay big advantages right here with the aid of making it handy to be mindful, define, and write the assessments that are crucial to qualify a board for pass/no-circulate status at manufacturing time.

    continually the steps to setting up these diagnostic assessments consist of:

  • Defining the vital interfaces/power that need to be functionally tested
  • Prioritizing these exams in keeping with circuit requirements.
  • selecting test coverage required for each examine.
  • establishing the assessments.
  • Checking the assessments on a prototype board.
  • generating the optimized run version of the diagnostic tests.
  • examine yield insurance will also be tuned in accordance with the customary requirements and perceived dangers for a selected board. typically, a hundred% test coverage of the hardware board isn't fiscally feasible because of the board diagnostic look at various building prices and run-time expenses incurred at creation time. for this reason, if the design has been confirmed to work, in quest of full hardware test insurance isn't imperative at creation testing because of lower inherent risk of the design.

    it is premier now not to have the same application developers who will increase the board SoC construction utility also write the diagnostic tests. at the beginning this seems counterproductive. considering the software builders recognize the hardware from their work, without doubt this can store time and resources through the use of them to jot down the hardware board diagnostic exams. however, really the opposite is correct.

    The utility designers who're very prevalent with the hardware can now and again be blinded into the use of the identical software implementations that work in production utility/firmware and inserting it within the diagnostic look at various code. The element of the diagnostic tests is to flush out advantage hardware issues. for this reason, having these assessments written by using someone other than the common application building crew will allow the look at various utility to handle the hardware in different ways that may and do reveal potential issues even before the production application is loaded and run.

    here's a different enviornment the place having early prototype boards is very crucial in view that they may also be used for early diagnostic examine building, which in flip improves the hardware design considering that the early assessments can flush out early error within the hardware design or mistaken implementations of the board necessities. The early prototype boards additionally provide the diagnostic exams an extra advantage of being troubleshooting courses for the application crew after they at last receive completely useful and tested circuit boards due to the fact that they could confer with these tests if they run into problems all the way through their development.

    The checks are usually written without a working gadget to be certain they have got fewer dependencies and supply less difficult hardware administration concepts. The ultimate step to the diagnostic check development is to optimize the assessments into runtime executable code that can also be run on each production board.

    it is critical not to pass this step due to the fact the per-unit examine time should be minimized for construction boards because each and every second of test time charges a specific amount. in spite of this, diagnostic testing is worth the can charge of construction and execution since it improves board yield. additionally, standard board manufacturability is superior for the reason that vital test time facts concerning the design can also be accompanied and sent to the board dressmaker for updates to the next edition of the board.

    Conclusion

    As can also be viewed from these examples, several steps in the PCB construction method could have more have an impact on on the manufacturability of the PCB. Having the abilities of those concerns and constructing a process for minimizing their abilities have an impact on can go a protracted approach toward expanding the manufacturability of a circuit board all the way through the design section of the mission.

    References

    Texas devices AM335x8 datasheet: https://killexams.com/language-exams

    JEDEC normal J-STD-020D.1

    Damon Domke is a senior hardware design engineer at Texas contraptions (TI), the place he is at the moment designing contrast modules and verify boards for the Sitara processor platform. he is a member of the group Technical team of workers at TI. He has worked the past 24 years constructing embedded processor-based circuit boards, FPGA construction techniques, and application/firmware applied sciences. He earned a master of science degree in electrical engineering and computer science from the institution of California, Irvine.


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